1. Technical Field
The present invention relates to data processing systems and more particularly, to a method and apparatus for controlling data transfers between a data processing unit and a cache.
2. Background Art
A cache is a relatively high-speed, small, local memory which is used to provide a local storage for frequently accessed memory locations of a larger, relatively slow, main memory. By storing a duplicate copy of the most frequently used main memory information locally, the cache is able to rapidly respond to most memory references, thus avoiding the accessing of the slower main memory. The result is lower traffic on the memory bus and decreased latency on the local bus to the requesting data processing unit. In a multiprocessing system, the use of a cache also increases potential systems' performance by reducing each data processing unit's demand for system bus bandwidth, thus allowing more data processing units in the system.
The above-identified copending patent application Ser. No. 890,859, of David Johnson, et al. discloses a cache directory which is capable of being configured into a plurality of ways, each way including tag and valid-bit storage for associatively searching the directory for cache data-array addresses. A cache configuration register splits the cache directory into two or more logical directories which are able to control requests from two or more data processing units.
In the above-identified Johnson, et al. system, if an access results in a cache-read miss, the cache line (four words) is first updated with the data from main memory, and then the data is transferred from the cache to the data processing unit. This automatically results in four additional wait states for the data processing unit access in addition to any memory-latency wait states. The result is reduced performance and decreased bus bandwidth.
If the data processing unit's copy of the data is updated first and then the cache's copy of the data is updated, the cache will have to arbitrate for the bus in order to prevent the data processing unit from beginning another access while the cache is being updated. This would improve access latency, but would still decrease bus bandwidth.
If the system simultaneously tries to transfer data to the data processing unit and cache, the data processing unit may attempt another access before the cache is completely updated. For example, consider the situation where the data processing unit requests only the first word of the four-word line. The update of the cache line requires all four words, so while the last three words are being transferred to the cache only, the data processing unit may try to access the memory.
It is an object of the present invention to provide circuitry to improve the performance of a data processing unit which uses burst mode (multiple word) accesses to memory during a cache miss.